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MC34065-H, L MC33065-H, L High Performance Dual Channel Current Mode Controllers
The MC34065-H,L series are high performance, fixed frequency, dual current mode controllers. They are specifically designed for off-line and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature a unique oscillator for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, Drive Output 2 Enable pin, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, and a latch for single pulse metering of each output. These devices are available in dual-in-line and surface mount packages. The MC34065-H has UVLO thresholds of 14 V (on) and 10 V (off), ideally suited for off-line converters. The MC34065-L is tailored for lower voltage applications having UVLO thresholds of 8.4 V (on) and 7.8 V (off). * Unique Oscillator for Precise Duty Cycle Limit and Frequency Control * Current Mode Operation to 500 kHz * Automatic Feed Forward Compensation * Separate Latching PWMs for Cycle-By-Cycle Current Limiting * Internally Trimmed Reference with Undervoltage Lockout * Drive Output 2 Enable Pin * Two High Current Totem Pole Outputs * Input Undervoltage Lockout with Hysteresis * Low Startup and Operating Current
VCC 5.0V Reference
R 16
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HIGH PERFORMANCE DUAL CHANNEL CURRENT MODE CONTROLLERS SEMICONDUCTOR TECHNICAL DATA
P SUFFIX PLASTIC PACKAGE 16 CASE 648 1 DW SUFFIX PLASTIC PACKAGE CASE 751G (SO-16L)
16 1
PIN CONNECTIONS
Sync Input CT RT Voltage Feedback 1 Compensation 1 Current Sense 1 Drive Output 1 Gnd 1 2 3 4 5 6 7 8 (Top View) 16 VCC 15 Vref 14 Drive Output 2 Enable 13 Voltage Feedback 2 12 Compensation 2 11 Current Sense 2 10 Drive Output 2 9 Drive Gnd
Vref
1 5 1
VCC Undervoltage Lockout
R
Sync Input RT CT 3 Oscillator 2 Voltage Feedback 1 Compensation 1 5 Drive Output 2 Enable 14 Voltage Feedback 2 13 Compensation 2 12 + - Error Amp 2 + - Error Amp 1
Vref Undervoltage Lockout Drive Output 1 Latching PWM 1 7
ORDERING INFORMATION
Current Sense 61
4
Device MC34065DW-H MC34065DW-L MC34065P-H MC34065P-L MC33065DW-H MC33065DW-L MC33065P-H MC33065P-L
Operating Temperature Range
Package SO-16L
Drive Output 2 Latching PWM 2 10
TA = 0 to +70C
Plastic DIP SO-16L
Current Sense 11 2 Gnd 8 Drive Gnd 9
TA = -40 to +85C
Plastic DIP
Representative Block Diagram
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 2
1
Publication Order Number: MC34065-H/D
MC34065-H, L
MAXIMUM RATINGS
Rating Power Supply Voltage Output Current, Source or Sink (Note 1) Output Energy (Capacitive Load per Cycle) Current Sense, Enable, and Voltage Feedback Inputs Sync Input High State (Voltage) Low State (Reverse Current) Error Amp Output Sink Current Power Dissipation and Thermal Characteristics DW Suffix, Plastic Package Case 751G Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air P Suffix, Plastic Package Case 648 Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature (Note 3) MC34065 MC33065 Storage Temperature Range values TA is the operating ambient temperature range that applies to [Note 3].) Characteristics REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25C) Line Regulation (VCC = 11 V to 20 V) Load Regulation (IO = 1.0 mA to 10 mA, VCC = 20 V) Total Output Variation over Line, Load, and Temperature Output Short Circuit Current OSCILLATOR AND PWM SECTIONS Total Frequency Variation over Line and Temperature VCC = 11 V to 20 V, TA = Tlow to Thigh MC34065 MC33065 Frequency Change with Voltage (VCC = 11 V to 20 V) Duty Cycle at each Output Maximum Minimum Sync Input Current High State (Vin = 2.4 V) Low State (Vin = 0.8 V) ERROR AMPLIFIERS Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 5.0 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25C) Power Supply Rejection Ratio (VCC = 11 V to 20 V) VFB IIB AVOL BW PSRR 2.45 - 65 0.7 60 2.5 - 0.1 100 1.0 90 2.55 - 1.0 - - - V A dB MHz dB fosc 46.5 45 fosc/V DCmax DCmin IIH IIL - 46 - - - 49 49 0.2 49.5 - 170 80 51.5 53 1.0 52 0 250 160 % % kHz Vref Regline Regload Vref ISC 4.85 - - 4.8 30 5.0 2.0 3.0 - 100 5.13 20 25 5.15 - V mV mV V mA Symbol VCC IO W Vin VIH IIL IO Value 20 400 5.0 - 0.3 to +5.5 +5.5 - 5.0 10 Unit V mA J V V mA mA
PD RJA PD RJA TJ TA
862 145
mW C/W mW C/W C C
1.25 100 +150 0 to +70 - 40 to +85 - 65 to +150
Tstg
C
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 8.2 k, CT = 3.3 nF, for typical values TA = 25C, for min/max
Symbol
Min
Typ
Max
Unit
A
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MC34065-H, L
ERROR AMPLIFIERS Output Current Source (VO = 3.0 V, VFB = 2.3 V) Sink (VO = 1.2 V, VFB = 2.7 V) Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) Isource Isink VOH VOL 0.45 2.0 5.0 - 1.0 12 6.2 0.8 - - - 1.1 mA
V
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MC34065-H, L
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 8.2 k, CT = 3.3 nF, for typical values TA = 25C, for min/max
values TA is the operating ambient temperature range that applies to [Note 3].) Characteristics CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 4 and 5) Maximum Current Sense Input Threshold (Note 4) Input Bias Current Propagation Delay (Current Sense Input to Output) DRIVE OUTPUT 2 ENABLE PIN Enable Pin Voltage - High State (Output 2 Enabled) Enable Pin Voltage - Low State (Output 2 Disabled) Low State Input Current (VIL = 0 V) DRIVE OUTPUTS Output Voltage - Low State (Isink = 20 mA) Output Voltage - Low State (Isink = 200 mA) Output Voltage - High State (Isource = 20 mA) Output Voltage - High State (Isource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) Output Voltage Rise Time (CL = 1.0 nF) Output Voltage Fall Time (CL = 1.0 nF) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC Increasing) -L Suffix -H Suffix Minimum Operating Voltage After Turn-On (VCC Decreasing) -L Suffix -H Suffix TOTAL DEVICE Power Supply Current Startup -L Suffix (VCC = 6.0 V) -H Suffix (VCC = 12 V) Operating (Note 2) ICC - - - 0.4 0.6 20 0.8 1.0 25 mA Vth V 7.8 13 7.2 9.0 8.4 14 7.8 10 9.0 15 V 8.4 11 VOL VOH VOL(UVLO) tr tf - 1.6 12.8 10 - - - 0.3 2.4 13.3 11.2 0.1 50 50 0.5 3.0 - 12.3 1.1 150 150 V VIH VIL IIB 3.5 0 100 - - 250 Vref 1.5 400 V A AV Vth IIB tPLN(In/Out) 2.75 0.9 - - 3.0 1.0 - 2.0 150 3.25 1.1 - 10 300 V/V V A ns
Symbol
Min
Typ
Max
Unit
V ns ns
VCC(min)
4. This parameter is measured at the latch trip point with VFB = 0 V NOTES: 1. Maximum package power dissipation limits must be observed. NOTES: 2. Adjust VCC above the startup threshold before setting to 15 V. V Compensation NOTES: 3. Low duty cycle pulse techniques are used during test to maintain junction 5. Comparator gain is defined as AV = V Current Sense NOTES: 3. temperature as close to ambient as possible: Thigh = +70C for MC34065 Tlow = 0C for the MC34065 Thigh = +85C for MC33065 Tlow = -40C for the MC33065
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MC34065-H, L
16 R T, TIMING RESISTOR (k ) 14 12 10
5.0 nF 3.3 nF 1.0 nF 100 pF 500 pF 220 pF
50 DC max , DUTY CYCLE MAXIMUM (%) 48 46 44 42 40 38 30 k 50 k 100 k 300 k 500 k fOSC, OSCILLATOR FREQUENCY (Hz) 1.0 M 10 k 30 k 50 k 100 k 300 k 500 k fOSC, OSCILLATOR FREQUENCY (Hz) 1.0 M VCC = 15 V RT = 4.0 k to 16 k TA = 25 CL = 15 pF Output 1 Output 2
330 pF 2.2 nF
8.0 6.0 4.0
CT = 10 nF VCC = 15 V TA = 25C
10 k
Figure 1. Timing Resistor versus Oscillator Frequency
Figure 2. Maximum Output Duty Cycle versus Oscillator Frequency
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MC34065-H, L
VCC = 15 V AV = -1.0 TA = 25C 20 mV/DIV VCC = 15 V AV = -1.0 TA = 25C 200 mV/DIV 1.0 s/DIV
2.55 V
3.0 V
2.50 V
2.50 V
2.45 V 1.0 s/DIV
2.0 V
Figure 3. Error Amp Small-Signal Transient Response
Figure 4. Error Amp Large-Signal Transient Response
Vth, CURRENT SENSE INPUT THRESHOLD (V)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
100 80 60 40 20 0 -20 10 Gain VCC = 15 V VO = 1.5 V to 2.5 V RL = 100 k TA = 25C
0 , EXCESS PHASE (DEGREES) 30 60 90 Phase 120 150 180 10 M
1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 VO, ERROR AMP OUTPUT VOLTAGE (V) VCC = 15 V TA = 125C TA = 25C TA = -55C
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
Figure 5. Error Amp Open Loop Gain and Phase versus Frequency
Figure 6. Current Sense Input Threshold versus Error Amp Output Voltage
0 VCC = 15 V
ISC , REFERENCE SHORT CIRCUIT CURRENT (mA)
Vref, REFERENCE VOLTAGE CHANGE (mV)
120 VCC = 15 V RL 0.1 100
-4.0 -8.0 -12 -16 TA = 125C -20 -24 0 20 40 60 80 100 120 TA = 25C TA = -55C
80
60 -55
-25
Iref, REFERENCE SOURCE CURRENT (mA)
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 7. Reference Voltage Change versus Source Current
Figure 8. Reference Short Circuit Current versus Temperature
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MC34065-H, L
VO , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) VCC = 15 V IO = 1.0 mA to 10 mA TA = 25C VO, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VCC = 11 V to 15 V TA = 25C
1.0 ms/DIV
1.0 ms/DIV
Figure 9. Reference Load Regulation
Figure 10. Reference Line Regulation
Vsat , OUTPUT SATURATION VOLTAGE (V)
0 VCC Source Saturation VCC = 15 V (Load to Ground) 80 s Pulsed Load 120 Hz Rate TA = 25C TA = -55C VCC = 15 V CL = 1.0 nF TA = 25C
-2.0 -4.0 -6.0 4.0 2.0 0 0
90% -
TA = -55C TA = 25C Gnd
Sink Saturation (Load to VCC) 400
10% -
100 200 300 IO, OUTPUT LOAD CURRENT (mA)
100 ns/DIV
Figure 11. Output Saturation Voltage versus Load Current
Figure 12. Output Waveform
VO2, OUTPUT VOLTAGE 2; VO1, OUTPUT VOLTAGE 1 ICC, SUPPLY CURRENT
32 10 V/DIV 50 mA/DIV 10 V/DIV ICC , SUPPLY CURRENT (mA)
24
VCC = 15 V CL = 15 pF TA = 25C
RT = 10 k CT = 3.3 nF VFB = 0 V Current Sense = 0 V TA = 25C
16 -L Suffix -H Suffix 8.0
100 ns/DIV
0 0
4.0
8.0
12
16
20
VCC, SUPPLY VOLTAGE (V)
Figure 13. Output Cross Conduction Current
Figure 14. Supply Current versus Supply Voltage
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MC34065-H, L
OPERATING DESCRIPTION The MC34065-H,L series are high performance, fixed frequency, dual channel current mode controllers specifically designed for Off-Line and dc-to-dc converter applications. These devices offer the designer a cost effective solution with minimal external components where independent regulation of two power converters is required. The Representative Block Diagram is shown in Figure 15. Each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. The oscillator, reference regulator, and undervoltage lock-out circuits are common to both channels.
Oscillator
The unique oscillator configuration employed features precise frequency and duty cycle control. The frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink, generating a symmetrical 50 percent duty cycle waveform at Pin 2. The oscillator peak and valley thresholds are 3.5 V and 1.6 V respectively. The source/sink current magnitude is controlled by resistor RT. For proper operation over temperature it must be in the range of 4.0 k to 16 k as shown in Figure 1. As CT charges and discharges, an internal blanking pulse is generated that alternately drives the center inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non-overlapping output duty cycles. Output 2 is enabled while CT is charging, and Output 1 is enabled during the discharge. Figure 2 shows the Maximum Output Duty Cycle versus Oscillator Frequency. Note that even at 500 kHz, each output is capable of approximately 44% on-time, making this controller suitable for high frequency power conversion applications. In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal as shown in Figure 17. For reliable locking, the free-running oscillator frequency should be set about 10% less than the clock frequency. Referring to the timing diagram shown in Figure 16, the rising edge of the clock signal applied to the Sync input, terminates charging of CT and Drive Output 2 conduction. By tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. A circuit method for this, and multi-unit synchronization, is shown in Figure 18.
Error Amplifier
(Figure 5). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. The maximum input bias current is -1.0 A which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp output (Pin 5, 12) is provided for external loop compensation. The output voltage is offset by two diode drops (1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no pulses appear at the Drive Output (Pin 7, 10) when the error amplifier output is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figures 20, 21). The minimum allowable Error Amp feedback resistance is limited by the amplifier's source current (0.5 mA) and the output voltage (VOH) required to reach the comparator's 1.0 V clamp level with the inverting input at ground. This condition happens during initial system startup or when the sensed output is shorted:
Rf(min) 3.0 (1.0 V) ) 1.4 V = 8800 0.5 mA
Current Sense Comparator and PWM Latch
The MC34065 operates as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier output. Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator-PWM Latch configuration used ensures that only a single pulse appears at the Drive Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting a ground-referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 6, 11) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 5, 12 where:
Ipk = V(Pin 5, 12) - 1.4 V 3 RS
Each channel contains a fully-compensated Error Amplifier with access to the inverting input and output. The amplifier features a typical dc voltage gain of 100 dB, and a unity gain bandwidth of 1.0 MHz with 71 of phase margin
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:
Ipk(max) = 1.0 V RS
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MC34065-H, L
When designing a high power switching regulator it may be desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 19. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense input with a time constant that approximates the spike duration will usually eliminate the instability, refer to Figure 24.
Undervoltage Lockout
hysteresis and low startup current of the -H suffix version makes it ideally suited in off-line converter applications where efficient bootstrap startup techniques are required (Figure 28). The -L suffix version is intended for lower voltage dc-to-dc converter applications. The minimum operating voltage for the -H suffix is 11 V and 8.2 V for the -L suffix.
Drive Outputs and Drive Ground
Two Undervoltage Lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stages are enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 14 V/10 V for -H suffix, and 8.4 V/7.6 V for -L suffix. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V respectively. The large
Each section contains a single totem-pole output stage that is specifically designed for direct drive of power MOSFETs. The Drive Outputs are capable of up to 400 mA peak current with a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the outputs in a sinking mode whenever an Undervoltage Lockout is active. This characteristic eliminates the need for an external pull-down resistor. The totem-pole output has been optimized to minimize cross-conduction current in high speed operation. The addition of two 10 resistors, one in series with the source output transistor and one in series with the sink output transistor, reduces the cross-conduction current to minimal levels, as shown in Figure 13. Although the Drive Outputs were optimized for MOSFETs, they can easily supply the negative base current required by bipolar NPN transistors for enhanced turn-off (Figure 25).
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MC34065-H, L
Vin = 15V
VCC
16
Vref 15 2.5V R R Sync Input 1 3 CT 2
1.0mA
Reference Regulator Internal Bias 20k 3.6V Oscillator PWM Latch 1 Current Sense Comparator 1 2R - + 1.0V R R S Q + - + -
VCC UVLO
+ -
+ -
Vref UVLO 10 Drive Output 1 10 7 Q1
RT
Voltage Feedback 1 4
+ - Error Amp 1
Current Sense 1 6
Compensation 15
Vref
250A
RS 10 Drive Output 2 Q2
Enable Input 14
1.0mA
PWM Latch 2 2R Current Sense Comparator 2 - + 1.0V R S R R Q
10 10
Voltage Feedback 2 13
+ - Error Amp 2
Current Sense 2 11 RS
Compensation 2 12 Gnd 8 Drive Gnd 9 + - =
Sink Only Positive True Logic
Figure 15. Representative Block Diagram
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MC34065-H, L
Sync Input
Capacitor CT
Latch 1 Set" Input Compensation 1 Current Sense 1 Latch 1 Reset" Input
Drive Output 1
Drive Output 2 Enable Latch 2 Set" Input Compensation 2 Current Sense 2 Latch 2 Reset" Input
Drive Output 2
Figure 16. Timing Diagram
The outputs do not contain internal current limiting, therefore an external series resistor may be required to prevent the peak output current from exceeding the 400 mA maximum rating. The sink saturation (VOL) is less than 0.75 V at 50 mA. A separate Drive Ground pin is provided and, with proper implementation, will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. Figure 23 shows the proper ground connections required for current sensing power MOSFET applications.
Drive Output 2 Enable Pin
protection and is capable of providing in excess of 30 mA for powering any additional control system circuitry.
Design Considerations
This input is used to enable Drive Output 2. Drive Output 1 can be used to control circuitry that must run continuously such as volatile memory and the system clock, or a remote controlled receiver, while Drive Output 2 controls the high power circuitry that is occasionally turned off.
Reference
The 5.0 V bandgap reference is trimmed to 2.0% tolerance at TJ = 25C. The reference has short circuit
Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse-width jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 F) connected directly to VCC and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage-divider should be located close to the IC and as far as possible from the power switch and other noise generating components.
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MC34065-H, L
Vref 1 5 R Bias R 220p F 1 20k 6 8 5.0k + - 5.0k 2 + - 5.0k 4 + - 5 EA1 2R 1.0V R C f= 1.08 (RA + RB)C RB RA + RB To additional MC34065s Dmax Drive Output 2 = RA RA + RB 5 1 S MC1455 RB 4 + - 2R EA1 1.0V R R Q 3 2 3 Osc. 4 7 RA R 1 20k 15 R Bias
External Sync Input
3 RT CT Osc .
5
2
The external diode clamp is required if the negative Sync current is greater than -5.0 mA.
Dmax Drive Output 1 =
Figure 17. External Clock Synchronization
Figure 18. External Duty Cycle Clamp and Multi-Unit Synchronization
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Sync Input CT RT Voltage Feedback 1 Compensation 1 Current Sense 1 Drive Output 1 Gnd Drive Gnd Drive Output 2 Current Sense 2 Compensation 2 Voltage Feedback 2 Drive Output 2 Enable Vref VCC Description A narrow rectangular waveform applied to this input will synchronize the oscillator. A dc voltage within the range of 2.4 V to 5.5 V will inhibit the oscillator. Timing capacitor CT connects from this pin to ground setting the free-running oscillator frequency range. Resistor RT connects from this pin to ground precisely setting the charge current for CT. RT must be between 4.0 k and 16 k. This pin is the inverting input of Error Amplifier 1. It is normally connected to the switching power supply output through a resistor divider. This pin is the output of Error Amplifier 1 and is made available for loop compensation. A voltage proportional to the inductor current is connected to this input. PWM 1 uses this information to terminate conduction of output switch Q1. This pin directly drives the gate of a power MOSFET Q1. Peak currents up to 400 mA are sourced and sunk by this pin. This pin is the control circuitry ground return and is connected back to the source ground. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This pin directly drives the gate of a power MOSFET Q2. Peak currents up to 400 mA are sourced and sunk by this pin. A voltage proportional to inductor current is connected to this input. PWM 2 uses this information to terminate conduction of output switch Q2. This pin is the output of Error Amplifier 2 and is made available for loop compensation. This pin is the inverting input of Error Amplifier 2. It is normally connected to the switching power supply output through a resistor divider. A logic low at this input disables Drive Output 2. This is the 5.0 V reference output. It can provide bias for any additional system circuitry. This pin is the positive supply of the control IC. The minimum operating voltage range after startup is 11 V to 15.5 V for the -H suffix, 8.2 V to 9.5 V for the -L suffix.
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MC34065-H, L
VCC 16 Vref 1 5 R Bias R 1 3 Osc. 2 1.0mA + - EA1 2R 1.0V R1 5 VClamp 1.67 + 0.33 x 10-3 (R1) R2 )1 R1 Ipk(max) VClamp RS R 6 RS 5 C tSoft-Start 2100 C in F 1.0M VClamp - + R 4 + - EA1 2R 1.0V R PWM Latch 1 S Q 2 7 20k + +- _ 1 3 Osc. 1.0mA 5.0Vref + - + _ Vref 15 R Bias R Q1 20k Vin
4 R2
Where: 0 VClamp 1.0 V
Figure 19. Adjustable Reduction of Clamp Level
VCC 16 Vref 15 5.0Vref R Bias R 1 3 Osc 2 4 + - EA1 R2 C R1 5 MPSA63 VClamp 1.67 R2 R1 )1 tSoft-Start = In 1- 1 VC 3 VClamp 2R 1.0V VClamp - + R Ipk(max) VClamp RS C R 1R 2 R1 ) R2 6 RS PWM Latch 1 S Q R 7 - + 20k + _ + - + -+ _ 5.0Vref + + - Q1 - Vin
Figure 20. Soft-Start Circuit
VCC 16 + - + _ Vin
Rg PWM Latch 1 S Q R 7 Q1 D1 1N5819
6
RS
Where: 0 VClamp 1.0 V
Series gate resistor Rg may be needed to damp high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Rg will decrease the MOSFET switching speed. Schottky diode D1 is required if circuit ringing drives the output pin below ground.
Figure 21. Adjustable Reduction of Clamp Level with Soft-Start
VCC 16 + _ + _ Vin
Figure 22. MOSFET Parasitic Oscillations
VCC 16
Vin
5.0Vref
+ _ D G
5.0Vref + _
+ _
+ _
+ _
- +
PWM Latch 1 S Q R
7
M
SENSEFET S Power Ground to Input Source Return K Drive Ground to Pin 9 VPin 6 RS Ipk rDS(on) rDM(on) + RS - +
+ _
Q1 PWM Latch 1 S Q R 7
6 Control Circuitry Ground to Pin 8
RS 1/4W
If: SENSEFET = MTP10N10M RS = 200 Then: VPin 6 = 0.075 Ipk
R 6 C RS
Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 19 and 21.
The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform.
Figure 23. Current Sensing Power MOSFET http://onsemi.com
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Figure 24. Current Waveform Spike Suppression
MC34065-H, L
IB + 0 - Base Charge Removal C1 5.0Vref + +- - PWM Latch 1 S Q R 7 + - + _ 16 Vin VCC Vin
Isolation Boundary Q1 D1
RS
- +
6 * 1.4 N S N C P S
R NS NP
The totem-pole outputs can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1.
(Pin 6) I pk + 3R
V
Figure 25. Bipolar Transistor Drive
Figure 26. Isolated MOSFET Drive
VCC = 15V 16 + 47
15
5.0Vref 2.5V R R Bias + 20k +- _
+ - + _
1 3 Osc. 12k 1.0nF 2 1.0mA 4 + - 5 EA1
10 PWM Latch 1 S 2R - + 1.0V R R 6 Q 10 7
27
10 +
1N5819 +VO 2.0 VCC + 47 R2 R1
Connect to Pin 4 for closed-loop regulation.
)V 250A 10 14 1.0mA + 13 - EA2 1.0V 12 8 9 R 11 2R - + PWM Latch 2 S RQ R 10 10 27 10 +
O
+ 2.5 1N5819
R2 R1
)1
-VO -VCC 47 +
Output Load Regulation IO (mA) 0 1.0 5.0 10 50 +VO (V) 28.43 27.72 27.04 26.20 20.52 -VO (V) -13.89 -12.90 -12.25 -11.44 -5.80
The capacitor's equivalent series resistance must limit the Drive Output current to 400 mA. An additional series resistor may be required when using tantalum or other low ESR capacitors. The positive output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 27. Dual Charge Pump Converter
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MC34065-H, L
10 Cold <1 Hot T 92Vac to 138Vac 3.0A 0.22 T1 0.05 MDA 970G5
+ 270 56k L1 + 1N4148 10 RTN 9.0V 0.1A
MUR110 100 +
T2
MUR110 220 +
16 75k 5.0Vref R Bias 1 3 5.6k 4.7 nF Osc. 2 4 16.2k 1.0M 100 pF 5 1/2 4N35 14 47k 4.7k 47k 13 180 pF 12 8 9 + - EA2 1.0V R 2R - + S RQ R 10 PWM Latch 2 10 + - EA1 1.0V R 2R - + R 20k + _ + - + - + _
10k T3 330 pF 10 12k MTD 2N50 3300 pF 1N 4937 6 1.0 k 470 pF 3.3
MUR415 + 0.001 10 MUR415 1000
L3
330 + 330 10 RTN 10 12V 1.0A
15
1000 + L4 0.01
22 7
1/2 4N35
+ -12V 1.0A 100V 1.0A
PWM Latch 1 S Q R
10
MUR 440 100 0.001
L2 MPS + A20
68k 3.3k TL 43A 0.01
51k 100 1.3k
+
RTN
10k Output 2 Shutdown
10
22
MTH 8N45
11
1.0k 470pF 0.082
MC34065-H
Test Line Regulation 100 V Output 12 V Outputs 9.0 V Output Load Regulation 100 V Output 12 V Outputs 9.0 V Output Output Ripple 100 V Output 12 V Outputs 9.0 V Output Short Circuit Current 100 V Output 12 V Outputs 9.0 V Output Efficiency
Conditions Vin = 92 Vac to 138 Vac IO = 1.0 A IO = 1.0 A IO = 0.1 A Vin = 115 Vac IO = 0.25 A to 1.0 A IO = 0.25 A to 1.0 A IO = 0.08 A to 0.1 A Vin = 115 Vac IO = 1.0 A IO = 1.0 A IO = 0.1 A Vin = 115 Vac, RL = 0.1
Results = 40 mV or 0.02% = 32 mV or 0.13% = 55 mV or 0.31% = 50 mV or 0.025% = 320 mV or 1.2% = 234 mV or 1.3% 40 mVpp 100 mVpp 60 mVpp 4.3 A 17 A Output Hiccups 86 %
T1 - T2 -
468 H per section at 2.5 A, Coilcraft E3496A. Primary: 156 Turns, #34 AWG Primary Feedback: 19 Turns, #34 AWG Secondary: 17 Turns, #28 AWG Core: TDK PC30 EE22-Z Bobbin: BE22-118CP Gap: 0.001 for a primary inductance of 6.8 mH Primary: 56 Turns, #23 AWG (2 strands) Bifiliar Wound Secondary: 12 V, 4 Turns, #23 AWG (4 strands) Quadfiliar Wound Secondary 100 V: 32 Turns, #23 AWG (2 strands) Bifiliar Wound Core: TDK PC30 EER40 G0.76 Bobbin: BEER40-1112CP Gap: 0.030 for a primary inductance of 212 H 25 H at 1.0 A, Coilcraft Z7157. 10 H at 3.0 A, Coilcraft PCV-0-010-03.
T3 -
L1, L3, L4 - L2 -
Vin = 115 Vac, PO = 125 W
Figure 28. 125 Watt Off-Line Converter
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MC34065-H, L
5 11/16
4 1/2
(CIRCUIT VIEW)
AC INPUT
9V
*
100V
12V -12V
(COMPONENT VIEW) *100 V and 12 V Shutdown
Figure 29. PC Board Circuit Side and Component View
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MC34065-H, L
OUTLINE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H K G D
16 PL
SEATING PLANE
J TA
M
M
0.25 (0.010)
M
DW SUFFIX PLASTIC PACKAGE CASE 751G-03 (SOP-8+8L) ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45 _
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
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L
MC34065-H, L
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC34065-H/D

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